Amit Vahdat – Google’s vice president of system infrastructure mentioned, Google would use ‘SoC on the same chip or multiple chips in a package.’
To gradually replace ‘components integrated into a motherboard separated by a few inches of wires’, ‘SoC is the new motherboard’, this direction will be ‘Google’s next step.’
What Amit said, it sounds like Google was still using computers more than 20 years ago. There are various discrete functional chips on the motherboard. Google urgently needs to improve system integration to reduce the cost of interconnection circuits on the motherboard and improve performance. But is this the case?
We can see a single-socket motherboard with Intel Xeon server processors from a few years ago. Except for the processor slot and network chip that occupies the largest area in the middle, only various physical interfaces and power supplies remain on the entire motherboard Auxiliary devices such as management, resistance and capacitance.
The central Xeon integrates a multi-core processor with a display controller (GPU), a PCIE controller, and a DDR memory controller. The processor core integrates dedicated instruction modules for multimedia, compression, encryption, and almost all pure digital circuits. The logic has been integrated into the Intel processor.
Isn’t this an SoC – System on Chip? No matter what kind of SoC, the motherboard and physical signal interface will always exist. The server-level large-capacity memory is currently complex to fully integrate into the chip or package, so what we see is already a highly integrated, SoC-based processing Server system.
The statement that ‘SoC is the new motherboard’ is not accurate, and ‘Replacement of discrete functional components on the motherboard with SoC’ is a fact that has happened long ago. So what does the Google SoC innovation mentioned by Amit mean?
Let’s take a look at Amit’s blog post again. He mentioned Google’s self-developed TPU chip project (Tensor Processing Unit, oriented to AI acceleration, and has now developed to the third generation) that started in 2015, and Google’s VCU project (Video Coding) in 2018. Unit, for the accelerated processing of video streams,), and the 2019 OpenTitan project (open source security chip, based on the Titan chip), born from these projects, are precisely the “discrete functional components on the motherboard” mentioned by Amit, that is an available functional chip.
Google has already tasted the sweetness from the large-scale application of chips such as TPU. After combining Google’s software and AI algorithms, Google Translate, Google Colab, Google Image, and various customer applications deployed on Google Cloud are all used on a large scale. TPU chip.
When such a functional component chip achieves large-scale application success, what will Google do next?
Of course, as has happened repeatedly in the industry in the past 20 years, these new functional components are integrated into the processor SoC to reduce cost and power consumption further and improve integration. With the general-purpose processor market still firmly in the hands of manufacturers such as Intel, Google must consider designing its own SoC processors to accomplish its goals.
It is clear, The SoC innovation referred by Amit does not simply use SoC circuits to replace multiple discrete functional units on the motherboard. But starts from Google’s application requirements and goes beyond the existing general-purpose server SoC to customize and meet the diversified SoC processors for specific application requirements called “custom SoC processors”.
Similarly, the long-term goal of Mellanox, which Nvidia acquired in 2019, is to integrate Mellanox’s innovative SmartNIC functional modules into its new generation of SoC processors. Similarly, Amazon, Microsoft, Huawei, Alibaba, and other cloud vendors have already deployed their own SoC chip products and R&D teams.
Why are these system product giants focusing on small chips? Because future product innovation and competition will closely revolve around custom SoC chips, a complete system in a chip or package will have the most optimized performance and power consumption. Coupled with the close cooperation with the software system, it will give system product manufacturers Brings the most significant competitive advantage. The most typical example here is Apple, where chips, hardware systems, operating systems, and application systems are in full bloom.
Just as we have been used to seeing many customized SoCs in the embedded system field in the past, more customized processors will also be born in the field of desktop computers, cloud computing and servers.
Custom SoC processors represent the future of the entire chip industry: innovative functional chips are born from application system requirements. Then functional chips are absorbed by custom SoC processors, and even new innovative functions are directly integrated into SoC processors. This process will It will repeat again and again, and the cycle is getting faster and faster.
At the same time, the slower performance of general-purpose processors in recent years has also allowed the industry to lower the performance advantages of custom SoC processors gradually. It is the same reason that more expensive petroleum will promote the development of new energy.
However, custom SoC will require continuous optimization of the chip design cycle and design cost because the innovation of the terminal product company is based on the system-level optimization of software and hardware collaboration, and the cost reduction brought by this innovation is greater than the potential of profoundly optimized chip design. It is more important for the chip to be implemented and deployed into the product quickly and at a low cost.
The requirements mentioned above put forward higher requirements on the chip design and manufacturing industry chain and higher requirements on EDA manufacturers upstream of the chip industry chain. How to improve the current EDA process significantly, reduce the dependence on manual input, accelerate the chip design process, and reduce the cost of chip design. It is an opportunity for Chinese EDA companies.